|Opcode/Instruction||Op/En||64/32-bit Mode||CPUID Feature Flag||Description|
F2 0F F0 /r
LDDQU xmm1, mem
|RM||V/V||SSE3||Load unaligned data from mem and return double quadword in xmm1.|
VEX.128.F2.0F.WIG F0 /r
VLDDQU xmm1, m128
|RM||V/V||AVX||Load unaligned packed integer values from mem to xmm1.|
VEX.256.F2.0F.WIG F0 /r
VLDDQU ymm1, m256
|RM||V/V||AVX||Load unaligned packed integer values from mem to ymm1.|
|Op/En||Operand 1||Operand 2||Operand 3||Operand 4|
|RM||ModRM:reg (w)||ModRM:r/m (r)||NA||NA|
The instruction is functionally similar to (V)MOVDQU ymm/xmm, m256/m128 for loading from memory. That is: 32/16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched from memory and placed in a destination register (first operand). The source operand need not be aligned on a 32/16-byte boundary. Up to 64/32 bytes may be loaded from memory; this is implementation dependent.
This instruction may improve performance relative to (V)MOVDQU if the source operand crosses a cache line boundary. In situations that require the data loaded by (V)LDDQU be modified and stored to the same location, use (V)MOVDQU or (V)MOVDQA instead of (V)LDDQU. To move a double quadword to or from memory locations that are known to be aligned on 16-byte boundaries, use the (V)MOVDQA instruction.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
LDDQU (128-bit Legacy SSE version)
DEST[127:0] := SRC[127:0] DEST[MAXVL-1:128] (Unmodified)
VLDDQU (VEX.128 encoded version)
DEST[127:0] := SRC[127:0] DEST[MAXVL-1:128] := 0
VLDDQU (VEX.256 encoded version)
DEST[255:0] := SRC[255:0]
__m128i _mm_lddqu_si128 (__m128i * p);
VLDDQU: __m256i _mm256_lddqu_si256 (__m256i * p);
See Table 2-21, “Type 4 Class Exception Conditions”.
Note treatment of #AC varies.