VPDPBUSD — Multiply and Add Unsigned and Signed Bytes

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.0F38.W0 50 /r

A

V/V

AVX512_VNNI

Multiply groups of 4 pairs of signed bytes in

VPDPBUSD xmm1{k1}{z}, xmm2,

AVX512VL

xmm3/m128/m32bcst with corresponding

xmm3/m128/m32bcst

unsigned bytes of xmm2, summing those products and adding them to doubleword result in xmm1 under writemask k1.

EVEX.256.66.0F38.W0 50 /r

A

V/V

AVX512_VNNI

Multiply groups of 4 pairs of signed bytes in

VPDPBUSD ymm1{k1}{z}, ymm2,

AVX512VL

ymm3/m256/m32bcst with corresponding

ymm3/m256/m32bcst

unsigned bytes of ymm2, summing those products and adding them to doubleword result in ymm1 under writemask k1.

EVEX.512.66.0F38.W0 50 /r

A

V/V

AVX512_VNNI

Multiply groups of 4 pairs of signed bytes in

VPDPBUSD zmm1{k1}{z}, zmm2,

zmm3/m512/m32bcst with corresponding

zmm3/m512/m32bcst

unsigned bytes of zmm2, summing those products and adding them to doubleword result in zmm1 under writemask k1.

Instruction Operand Encoding

Op/En Tuple Operand 1 Operand 2 Operand 3 Operand 4
A Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA

Description

Multiplies the individual unsigned bytes of the first source operand by the corresponding signed bytes of the second source operand, producing intermediate signed word results. The word results are then summed and accumulated in the destination dword element size operand.

This instruction supports memory fault suppression.

Operation

VPDPBUSD dest, src1, src2

(KL,VL)=(4,128), (8,256), (16,512)

ORIGDEST := DEST

FOR i := 0 TO KL-1:

IF k1[i] or *no writemask*:

// Byte elements of SRC1 are zero-extended to 16b and

// byte elements of SRC2 are sign extended to 16b before multiplication.

IF SRC2 is memory and EVEX.b == 1:

t := SRC2.dword[0]

ELSE:

t := SRC2.dword[i]

p1word := ZERO_EXTEND(SRC1.byte[4*i]) * SIGN_EXTEND(t.byte[0])

p2word := ZERO_EXTEND(SRC1.byte[4*i+1]) * SIGN_EXTEND(t.byte[1])

p3word := ZERO_EXTEND(SRC1.byte[4*i+2]) * SIGN_EXTEND(t.byte[2])

p4word := ZERO_EXTEND(SRC1.byte[4*i+3]) * SIGN_EXTEND(t.byte[3])

DEST.dword[i] := ORIGDEST.dword[i] + p1word + p2word + p3word + p4word

ELSE IF *zeroing*:

DEST.dword[i] := 0

ELSE:

// Merge masking, dest element unchanged

DEST.dword[i] := ORIGDEST.dword[i]

DEST[MAX_VL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VPDPBUSD __m128i _mm_dpbusd_epi32(__m128i, __m128i, __m128i);

VPDPBUSD __m128i _mm_mask_dpbusd_epi32(__m128i, __mmask8, __m128i, __m128i);

VPDPBUSD __m128i _mm_maskz_dpbusd_epi32(__mmask8, __m128i, __m128i, __m128i);

VPDPBUSD __m256i _mm256_dpbusd_epi32(__m256i, __m256i, __m256i);

VPDPBUSD __m256i _mm256_mask_dpbusd_epi32(__m256i, __mmask8, __m256i, __m256i);

VPDPBUSD __m256i _mm256_maskz_dpbusd_epi32(__mmask8, __m256i, __m256i, __m256i);

VPDPBUSD __m512i _mm512_dpbusd_epi32(__m512i, __m512i, __m512i);

VPDPBUSD __m512i _mm512_mask_dpbusd_epi32(__m512i, __mmask16, __m512i, __m512i);

VPDPBUSD __m512i _mm512_maskz_dpbusd_epi32(__mmask16, __m512i, __m512i, __m512i);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-49, “Type E4 Class Exception Conditions”.