VGETMANTPD—Extract Float64 Vector of Normalized Mantissas from Float64 Vector

Opcode/

Op/

64/32

CPUID

Description

Instruction En bit Mode Support Feature Flag
EVEX.128.66.0F3A.W1 26 /r ib VGETMANTPD xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8 A V/V AVX512VL AVX512F Get Normalized Mantissa from float64 vector xmm2/m128/m64bcst and store the result in xmm1, using imm8 for sign control and mantissa interval normalization, under writemask.
EVEX.256.66.0F3A.W1 26 /r ib VGETMANTPD ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8 A V/V AVX512VL AVX512F Get Normalized Mantissa from float64 vector ymm2/m256/m64bcst and store the result in ymm1, using imm8 for sign control and mantissa interval normalization, under writemask.
EVEX.512.66.0F3A.W1 26 /r ib VGETMANTPD zmm1 {k1}{z}, zmm2/m512/m64bcst{sae}, imm8 A V/V AVX512F Get Normalized Mantissa from float64 vector zmm2/m512/m64bcst and store the result in zmm1, using imm8 for sign control and mantissa interval normalization, under writemask.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A Full ModRM:reg (w) ModRM:r/m (r) Imm8 NA

Description

Convert double-precision floating values in the source operand (the second operand) to DP FP values with the mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted results are written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.

The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.

7

imm8

6

5

Imm8[3:2] = 00b : sign(SRC)

Imm8[3:2] = 01b : 0

4

Imm8[3] = 1b : qNan_Indefinite if sign(SRC) != 0, regardless of imm8[2].

3 2 1

0

Imm8[1:0] = 00b : Interval is [ 1, 2)

Imm8[1:0] = 01b : Interval is [1/2, 2)

Imm8[1:0] = 10b : Interval is [ 1/2, 1)

Imm8[1:0] = 11b : Interval is [3/4, 3/2)

Sign Control (SC) Normaiization Interval Must Be Zero

Figure 5-15. Imm8 Controls for VGETMANTPD/SD/PS/SS

For each input DP FP value x, The conversion operation is:

GetMant(x) = ±2k|x.significand|

where:

1 <= |x.significand| < 2

Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is even or odd. The sign of the final result is determined by sc and the source sign.

If interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown in

Figure 5-15.

Each converted DP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a mantissa normalized to the range specified by interv.

The GetMant() function follows Table 5-7 when dealing with floating-point special numbers.

This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1 are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their previous values.

Note: EVEX.vvvv is reserved and must be 1111b; otherwise instructions will #UD.

Table 5-7. GetMant() Special Float Values Behavior

Input Result Exceptions / Comments
NaN QNaN(SRC) Ignore interv If (SRC = SNaN) then #IE
+∞ 1.0 Ignore interv
+0 1.0 Ignore interv
-0 IF (SC[0]) THEN +1.0 ELSE -1.0 Ignore interv
-∞ IF (SC[1]) THEN {QNaN_Indefinite} ELSE { IF (SC[0]) THEN +1.0 ELSE -1.0 Ignore interv If (SC[1]) then #IE
negative SC[1] ? QNaN_Indefinite : Getmant(SRC)1 If (SC[1]) then #IE

NOTES:

1. In case SC[1]==0, the sign of Getmant(SRC) is declared according to SC[0].

Operation

def getmant_fp64(src, sign_control, normalization_interval):

bias := 1023

dst.sign := sign_control[0] ? 0 : src.sign

signed_one := sign_control[0] ? +1.0 : -1.0

dst.exp := src.exp

dst.fraction := src.fraction

zero := (dst.exp = 0) and ((dst.fraction = 0) or (MXCSR.DAZ=1))

denormal := (dst.exp = 0) and (dst.fraction != 0) and (MXCSR.DAZ=0)

infinity := (dst.exp = 0x7FF) and (dst.fraction = 0)

nan := (dst.exp = 0x7FF) and (dst.fraction != 0)

src_signaling := src.fraction[51]

snan := nan and (src_signaling = 0)

positive := (src.sign = 0)

negative := (src.sign = 1)

if nan:

if snan:

MXCSR.IE := 1

return qnan(src)

if positive and (zero or infinity):

return 1.0

if negative:

if zero:

return signed_one

if infinity:

if sign_control[1]:

MXCSR.IE := 1

return QNaN_Indefinite

return signed_one

if sign_control[1]:

MXCSR.IE := 1

return QNaN_Indefinite

if denormal:

if MXCSR.DAZ:

dst.fraction := 0

else:

jbit := 0

dst.exp := bias

while jbit = 0:

jbit := dst.fraction[51]

dst.fraction := dst.fraction << 1

dst.exp : = dst.exp - 1

MXCSR.DE := 1

unbiased_exp := dst.exp - bias

odd_exp := unbiased_exp[0]

signaling_bit := dst.fraction[51]

if normalization_interval = 0b00:

dst.exp := bias

else if normalization_interval = 0b01:

dst.exp := odd_exp ? bias-1 : bias

else if normalization_interval = 0b10:

dst.exp := bias-1

else if normalization_interval = 0b11:

dst.exp := signaling_bit ? bias-1 : bias

return dst

VGETMANTPD (EVEX encoded versions)

VGETMANTPD dest{k1}, src, imm8

VL = 128, 256, or 512

KL := VL / 64

sign_control := imm8[3:2]

normalization_interval := imm8[1:0]

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

IF SRC is memory and (EVEX.b = 1):

tsrc := src.double[0]

ELSE:

tsrc := src.double[i]

DEST.double[i] := getmant_fp64(tsrc, sign_control, normalization_interval)

ELSE IF *zeroing*:

DEST.double[i] := 0

//else DEST.double[i] remains unchanged

DEST[MAX_VL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VGETMANTPD __m512d _mm512_getmant_pd( __m512d a, enum intv, enum sgn);

VGETMANTPD __m512d _mm512_mask_getmant_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn);

VGETMANTPD __m512d _mm512_maskz_getmant_pd( __mmask8 k, __m512d a, enum intv, enum sgn);

VGETMANTPD __m512d _mm512_getmant_round_pd( __m512d a, enum intv, enum sgn, int r);

VGETMANTPD __m512d _mm512_mask_getmant_round_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn, int r);

VGETMANTPD __m512d _mm512_maskz_getmant_round_pd( __mmask8 k, __m512d a, enum intv, enum sgn, int r);

VGETMANTPD __m256d _mm256_getmant_pd( __m256d a, enum intv, enum sgn);

VGETMANTPD __m256d _mm256_mask_getmant_pd(__m256d s, __mmask8 k, __m256d a, enum intv, enum sgn);

VGETMANTPD __m256d _mm256_maskz_getmant_pd( __mmask8 k, __m256d a, enum intv, enum sgn);

VGETMANTPD __m128d _mm_getmant_pd( __m128d a, enum intv, enum sgn);

VGETMANTPD __m128d _mm_mask_getmant_pd(__m128d s, __mmask8 k, __m128d a, enum intv, enum sgn);

VGETMANTPD __m128d _mm_maskz_getmant_pd( __mmask8 k, __m128d a, enum intv, enum sgn);

SIMD Floating-Point Exceptions

Denormal, Invalid

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions”; additionally:

#UD If EVEX.vvvv != 1111B.