VFPCLASSSD—Tests Types Of a Scalar Float64 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction En bit Mode Support Feature Flag
EVEX.LLIG.66.0F3A.W1 67 /r ib VFPCLASSSD k2 {k1}, xmm2/m64, imm8 A V/V AVX512DQ Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) NA NA

Description

The FPCLASSSD instruction checks the low double precision floating point value in the source operand for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result is written to the low bit in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.

The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category is listed in Table 5-4.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

CheckFPClassDP (tsrc[63:0], imm8[7:0]){

NegNum := tsrc[63];

IF (tsrc[62:52]=07FFh) Then ExpAllOnes := 1; FI;

IF (tsrc[62:52]=0h) Then ExpAllZeros := 1;

IF (ExpAllZeros AND MXCSR.DAZ) Then

MantAllZeros := 1;

ELSIF (tsrc[51:0]=0h) Then

MantAllZeros := 1;

FI;

ZeroNumber := ExpAllZeros AND MantAllZeros

SignalingBit := tsrc[51];

sNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaN

qNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaN

Pzero_res := NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0

Nzero_res := NegNum AND ExpAllZeros AND MantAllZeros; // -0

PInf_res := NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +Inf

NInf_res := NegNum AND ExpAllOnes AND MantAllZeros; // -Inf

Denorm_res := ExpAllZeros AND NOT(MantAllZeros); // denorm

FinNeg_res := NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite

bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR

( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR

( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR

( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );

Return bResult;

} //* end of CheckFPClassDP() *//

VFPCLASSSD (EVEX encoded version)

IF k1[0] OR *no writemask*

THEN DEST[0] :=

CheckFPClassDP(SRC1[63:0], imm8[7:0])

ELSE DEST[0] := 0

; zeroing-masking only

FI;

DEST[MAX_KL-1:1] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VFPCLASSSD __mmask8 _mm_fpclass_sd_mask( __m128d a, int c)

VFPCLASSSD __mmask8 _mm_mask_fpclass_sd_mask( __mmask8 m, __m128d a, int c)

SIMD Floating-Point Exceptions

None

Other Exceptions

See Table 2-53, “Type E6 Class Exception Conditions”; additionally:

#UD If EVEX.vvvv != 1111B.