|Instruction||En||Mode Support||Feature Flag|
NP 0F AE /3
|M||V/V||SSE||Store contents of MXCSR register to m32.|
VEX.LZ.0F.WIG AE /3
|M||V/V||AVX||Store contents of MXCSR register to m32.|
|Op/En||Operand 1||Operand 2||Operand 3||Operand 4|
Stores the contents of the MXCSR control and status register to the destination operand. The destination operand is a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
VEX.L must be 0, otherwise instructions will #UD.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
m32 := MXCSR;
See Table 2-22, “Type 5 Class Exception Conditions”; additionally:
If VEX.L= 1,
If VEX.vvvv ≠ 1111B.