MOVD/MOVQ—Move Doubleword/Move Quadword

Opcode/

Op/ En

64/32-bit

CPUID

Description

Instruction Mode Feature Flag

NP 0F 6E /r

MOVD mm, r/m32

A V/V MMX Move doubleword from r/m32 to mm.

NP REX.W + 0F 6E /r

MOVQ mm, r/m64

A V/N.E. MMX Move quadword from r/m64 to mm.

NP 0F 7E /r

MOVD r/m32, mm

B V/V MMX Move doubleword from mm to r/m32.

NP REX.W + 0F 7E /r

MOVQ r/m64, mm

B V/N.E. MMX Move quadword from mm to r/m64.

66 0F 6E /r

MOVD xmm, r/m32

A V/V SSE2 Move doubleword from r/m32 to xmm.

66 REX.W 0F 6E /r

MOVQ xmm, r/m64

A V/N.E. SSE2 Move quadword from r/m64 to xmm.

66 0F 7E /r

MOVD r/m32, xmm

B V/V SSE2 Move doubleword from xmm register to r/m32.

66 REX.W 0F 7E /r

MOVQ r/m64, xmm

B V/N.E. SSE2 Move quadword from xmm register to r/m64.

VEX.128.66.0F.W0 6E /

VMOVD xmm1, r32/m32

A V/V AVX Move doubleword from r/m32 to xmm1.

VEX.128.66.0F.W1 6E /r

VMOVQ xmm1, r64/m64

A V/N.E1. AVX Move quadword from r/m64 to xmm1.

VEX.128.66.0F.W0 7E /r

VMOVD r32/m32, xmm1

B V/V AVX Move doubleword from xmm1 register to r/m32.

VEX.128.66.0F.W1 7E /r

VMOVQ r64/m64, xmm1

B V/N.E1. AVX Move quadword from xmm1 register to r/m64.
EVEX.128.66.0F.W0 6E /r VMOVD xmm1, r32/m32 C V/V AVX512F Move doubleword from r/m32 to xmm1.
EVEX.128.66.0F.W1 6E /r VMOVQ xmm1, r64/m64 C V/N.E.1 AVX512F Move quadword from r/m64 to xmm1.
EVEX.128.66.0F.W0 7E /r VMOVD r32/m32, xmm1 D V/V AVX512F Move doubleword from xmm1 register to r/m32.
EVEX.128.66.0F.W1 7E /r VMOVQ r64/m64, xmm1 D V/N.E.1 AVX512F Move quadword from xmm1 register to r/m64.

NOTES: 1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-

sion is used.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A NA ModRM:reg (w) ModRM:r/m (r) NA NA
B NA ModRM:r/m (w) ModRM:reg (r) NA NA
C Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) NA NA
D Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) NA NA

Description

Copies a doubleword from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be general-purpose registers, MMX technology registers, XMM registers, or 32-bit memory locations. This instruction can be used to move a doubleword to and from the low doubleword of an MMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low doubleword of an XMM register and a general-purpose register or a 32-bit memory location. The instruction cannot be used to transfer data between MMX technology registers, between XMM registers, between general-purpose registers, or between memory locations.

When the destination operand is an MMX technology register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.

In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

MOVD/Q with XMM destination:

Moves a dword/qword integer from the source operand and stores it in the low 32/64-bits of the destination XMM register. The upper bits of the destination are zeroed. The source operand can be a 32/64-bit register or 32/64-bit memory location.

128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged. Qword operation requires the use of REX.W=1.

VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed. Qword operation requires the use of VEX.W=1.

EVEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed. Qword operation requires the use of EVEX.W=1.

MOVD/Q with 32/64 reg/mem destination:

Stores the low dword/qword of the source XMM register to 32/64-bit memory location or general-purpose register. Qword operation requires the use of REX.W=1, VEX.W=1, or EVEX.W=1.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

If VMOVD or VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception.

Operation

MOVD (when destination operand is MMX technology register)

    DEST[31:0] := SRC;
    DEST[63:32] := 00000000H;

MOVD (when destination operand is XMM register)

    DEST[31:0] := SRC;
    DEST[127:32] := 000000000000000000000000H;
    DEST[MAXVL-1:128] (Unmodified)

MOVD (when source operand is MMX technology or XMM register)

    DEST := SRC[31:0];

VMOVD (VEX-encoded version when destination is an XMM register)

    DEST[31:0] := SRC[31:0]
    DEST[MAXVL-1:32] := 0

MOVQ (when destination operand is XMM register)

    DEST[63:0] := SRC[63:0];
    DEST[127:64] := 0000000000000000H;
    DEST[MAXVL-1:128] (Unmodified)

MOVQ (when destination operand is r/m64)

    DEST[63:0] := SRC[63:0];

MOVQ (when source operand is XMM register or r/m64)

    DEST := SRC[63:0];

VMOVQ (VEX-encoded version when destination is an XMM register)

    DEST[63:0] := SRC[63:0]
    DEST[MAXVL-1:64] := 0

VMOVD (EVEX-encoded version when destination is an XMM register)

DEST[31:0] := SRC[31:0]
DEST[MAXVL-1:32] := 0

VMOVQ (EVEX-encoded version when destination is an XMM register)

DEST[63:0] := SRC[63:0]
DEST[MAXVL-1:64] := 0

Intel C/C++ Compiler Intrinsic Equivalent

MOVD:

__m64 _mm_cvtsi32_si64 (int i )

MOVD:

int _mm_cvtsi64_si32 ( __m64m )

MOVD:

__m128i _mm_cvtsi32_si128 (int a)

MOVD:

int _mm_cvtsi128_si32 ( __m128i a)

MOVQ:

__int64 _mm_cvtsi128_si64(__m128i);

MOVQ:

__m128i _mm_cvtsi64_si128(__int64);

VMOVD

__m128i _mm_cvtsi32_si128( int);

VMOVD

int _mm_cvtsi128_si32( __m128i );

VMOVQ

__m128i _mm_cvtsi64_si128 (__int64);

VMOVQ

__int64 _mm_cvtsi128_si64(__m128i );

VMOVQ

__m128i _mm_loadl_epi64( __m128i * s);

VMOVQ

void _mm_storel_epi64( __m128i * d, __m128i s);

Flags Affected

None

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-22, “Type 5 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-57, “Type E9NF Class Exception Conditions”.

Additionally:

#UD

If VEX.L = 1.

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.